1. Field of the Invention
The present invention relates to a field-effect transistor having a hyper-smooth face and a method for producing the same.
2. Description of the Related Art
In recent years, smoothing of hetero-interfaces has been energetically studied for the next generation electronic devices such as a further miniaturized MOS transistor and a quantum effect device.
Hereinafter, the hetero-interfaces of a conventional MOS field-effect transistor will be described with reference to the accompanying drawings. In the specification of the present invention, "MOS" is not limited to a three-layer structure consisting of metal-oxide film-semiconductor, but includes a three-layer structure of conductor-insulating film-semiconductor.
FIGS. 4A through 4C are cross sectional views illustrating a process of forming a conventional interface between silicon and an oxide film.
FIG. 4A shows a cross section of a silicon substrate 70 before formation of a gate insulting film in a MOS field-effect transistor. Typically, general, a processed layer (thickness: about 100 nm to 500 nm) damaged in various processes such as slicing or polishing is formed at the surface of the silicon substrate. The processed layer is removed by forming a thermal oxide film on the surface of the silicon substrate by wet oxidation, and treating the thermal oxide film with a hydrofluoric acid or the like. Before the wet oxidation, the silicon substrate is subjected to RCA cleaning in order to remove organic contamination from the surface of the silicon substrate. FIG. 4A shows the state of the surface of the silicon substrate 70 immediately after the thermal oxide film has been removed.
However, wet oxidation is not suitable for forming a very thin gate insulating film since the resulting oxidation rate is too fast. For this reason, it is apparently advantageous to perform dry oxidation where thermal oxidation is performed with a dry ambient gas in order to form the very thin gate insulating film. However, it is reported that the gate insulting film obtained by the dry oxidation presents problems of a low withstand voltage for insulation. It is believed that such deterioration of the withstand voltage is due to concaves and convexes at the interface between the gate insulating film and the silicon substrate (e.g., M. Niwa et al, J. Electrochem. Soc., 139(1992)901).
Next, as shown in FIG. 4B, a gate insulating film 71 (thickness: 10 nm) is formed by dry oxidation. The dry oxidation is performed by heating the silicon substrate 70 to about 900.degree. C. with a dry oxygen gas in an electric furnace. Furthermore, in order to remove oxide film defects such as pin holes from the gate insulating film 71, the silicon substrate 70 is subjected to an annealing treatment at 950.degree. C. with a dry nitrogen gas for 20 min.
Although all the mechanisms responsible for formation of concaves and convexes at the interface 72 between the gate insulating film 71 and the silicon substrate 70 have not been fully determined at present, it is believed that the size of the oxidizing species and the silanol group of the oxide film are significant factors in the formation of concaves and convexes.
O.sub.2 has a larger size than that of H.sub.2 O. In addition, a silanol group which can function as a structure relaxation agent is not present in the dry O.sub.2 gas. As a result, the oxidizing species (O.sub.2) is not randomly (uniformly) bonded with silicon atoms located on the silicon surface, but the oxidizing species is believed to enter from a (111) facet face having a longest net bond length into the inside portion and reacts with silicon atoms there. Accordingly, in the case of dry oxidation, a path for introducing the oxidizing species is formed in a specific portion on the surface of the silicon, and oxidation proceeds from the path before other portions. For this reason, when dry oxidation is performed, concaves and convexes are easily formed at the interface between the oxide film and the silicon substrate.
In the present examples, since the oxide film formed by the dry oxidation has a debye length of 15 nm, an initial process region of oxidation whose mechanisms have not all yet been fully determined, and a final phase of forming the film (i.e., forming the oxide film) in the vicinity of the silicon/oxide film interface is performed according to the Deal-Grove reaction mechanism.
For the reason described above, it is understood that the relatively large concaves and convexes on the surface of the silicon substrates shown in FIG. 4B are formed as a result of the oxidizing species entering from an easy access (i.e., the path such as the (111) facet) and the reaction with the silicon atoms being promoted.
As shown in FIG. 4A, relatively small concaves and convexes are present on the surface of the silicon substrate 70 before the dry oxidation, and various fine crystalline planes appear on the surface. Since oxidation rate on the crystalline planes are varied with plane directions, the interface 72 between the oxide film and the silicon substrate has a complex surface profile obtained as a result of combining the large concaves and convexes and the small ones.
After the gate insulating film is formed, as shown in FIG. 4C, a polysilicon layer 73 for functioning as a gate electrode is deposited on the gate insulating film 71 to form a MOS structure. An rms value of the concaves and convexes at the interface between the insulating film and the silicon substrate formed in such a manner is about 1.5 nm, according to a cross sectional observation through a transmissive electronic microscope.
However, in the above-mentioned structure, the concaves and convexes at the interface adversely causes electrons travelling in an inversion layer to be scattered, resulting in restriction of the operation speed of a device. When a MOS field-effect transistor is produced using the above-mentioned MOS structure and operated, an inversion layer 74 is formed in a portion approximate to the gate oxide film 71 in the silicon substrate 70 (i.e., in the vicinity of the surface of the silicon substrate 70). A high electric field is formed in the inversion layer 74, and electrons 75 in the inversion layer 74 travel in the inversion layer 74 at a high speed. At this point, the electrons 75 are scattered by the concaves and convexes on the surface of the silicon, resulting in reduction of field-effect mobility of the electrons.